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PE12316 Triple Incremental Encoder
February 6, 2003 Preliminary (Version 1.1)
Features:
* * * * * * * Functional and pincompatible with TI CF32006 / THCT12316 Three independent channels in one device Each channel compatible with PE12016 Available as IP-Core or within PLCC68 Package Interfaces three mechanisms / axes to data bus Pulse width measurement Frequency measurement
* * * * * * * * *
Cascadable 16-bit counters TTL compatible 5V and 3.3V Operation 8 Bit parallel tristatable Bus Simple read & write procedure High speed 20 MHz clock operation Direction discriminators identify & measure forward/backward rotation separate zero pulse input New Feature: Each channel extendable to 24 Bit
READY KLI-KLO1 63 62 KLI-KLO2 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 39 40 41 42 44
A3 RESET
Ua01 Ua02 Ua03
A0 RD
WE
6 5
NC
9 8
7
4
3 2 1
68
65 64
67 66
NC GND
NC VCC
CLK
A1 A2 CS GND D0 D1 VCC D2 D3 GND D4 D5 VCC D6 D7 GND NC
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 31 32 33 37 38 27 28 29 30 34 35 36 43 26
KLI-KLO3 CARRY1 BORROW1 CARRY2 BORROW2 CARRY3 BORROW3 GND VCC DOWN3 UP3 DOWN2 UP2 DOWN1 UP1 Ua23 Ua13
PE12316 PLCC68
Ua11
NC Ua21
Ua12
Ua22
M01 M11
M21
M02
NC M12
M22 M03
M13
M23 NC
NC
Figure 1 Pinout
NC Pins should be left open and not connected to the PCB. They are reserved for future upgrades.
Description:
The PE12316 TRIPLE INCREMENTAL ENCODER INTERFACE consists of three channels each, which can independently determine the direction of displacement of a mechanical or axis based device on two input signals from transducers in quadrature. Alternatively, each channel can measure a pulse width using a known clock rate, or a frequency, by counting input pulses over a known time interval. It includes three 16/24-bit counters which may also be used separately. The PE12316 may be cascaded between channels on one device or between devices to provide accuracy greater than 16/24-bits, and is designed for use in many microprocessor-based systems.
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PE12316 Triple Incremental Encoder
February 6, 2003 Preliminary (Version 1.1)
Availability:
The PE12316 is available as a replacement IC or Netlist IP Core, fully compatible with the TI CF32006 functionality. The replacement IC is packaged within the popular PLCC68. The IP Core can be targeted to any desired FPGA/CPLD or ASIC Technology and is delivered within the according netlist format. The database has been proven in a co-emulation together with the reference part by stimulating both devices with the same inputs and observing the identical results on the outputs.
Ressource Usage IP Core:
Gate count for ASIC approximately 7000 Gates. Technologies is For FPGAs a technology with at least 20.000 FPGA Gates like XCS20 from Xilinx needs to be chosen.
Enhancements over CF32006:
The PE12316 has 3 counters with 24 Bit internally. Therefore an additional addressline /A3 is introduced on pin 6 to select the Bits 1623 of each channel in conjunction with the other addressbits A0-A2. NOTE: If /A3 is left unconnected, PE12316 is identical to CF32006.
Differences:
The PE12316 has some slight changes: UA1X and UA2X are synchronized with the clock, eliminating the need to place a discrete ACT74 type Flipflop in front of these signals. Due to this feature a latency of one clock cycle is introduced, resulting worst case in a +/-1 counter difference.
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PE12316
PE12316 Triple Incremental Encoder
February 6, 2003 Preliminary (Version 1.1)
Applications:
The PE12316 enables mechanical devices to be interfaced with microprocessors. It may be used in many diverse applications, including robotics, tooling machines, elevators, conveyor belts and transport mechanisms. Since it contains three channels each PE12316 can support three measurements or axes of motion.
Architecture:
Within each channel there are four main elements: 1. The measurement and mode control logic generates up or down count pulses, internal signals I1 and I2, from: - Quadrature signals Ua1, Ua2 and zero pulse Ua0n* - Clock input - Mode controls M0n*, M1n* and M2n* 2. A 16-bit counter made up from two independently loadable 8-bit counters. 3. A 16-bit latch which "freezes" the counter value when required. 4. A multiplexer that allows the processor to read either upper or lower byte in the latch. Supporting the three channels: The control logic provides common microprocessor interface signals; the output multiplexer allows the processor to select data from one of the three channels and the threestate buffers place this data on the bus. * The suffix n is a placeholder for either channel 1, channel 2 or channel 3 and will be used in this manner throughout the whole document.
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PE12316
PE12316 Triple Incremental Encoder
February 6, 2003 Preliminary (Version 1.1)
Figure 2 Block Diagramm for 16 Bit Mode
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PE12316 Triple Incremental Encoder
February 6, 2003 Preliminary (Version 1.1)
Operation:
The eight modes of operation of the PE12316 are summarized in Table 1. The modes of the three channels can be selected independently.
Mode
M2n
M1n
M0n COUNTER
Mode Description
0
0
0
0
16-bit up/down counter (inhibits direction discriminator)
DIRECTION DISCRIMINATOR 1 0 0 1 Single count pulse synchronous with Ua1n rising in forward direction and Ua1n falling in backward direction.
2
0
1
0
Single count pulse synchronous with Ua2n rising in forward direction and Ua2n falling in backward direction.
3
0
1
1
Double count pulse synchronous with Ua1n rising and falling.
4
1
0
0
Double count pulse synchronous with Ua2n rising and falling.
5
1
0
1
Quadruple count pulse synchronous with all edges.
PULSE WIDTH MEASUREMENT 6 1 1 0 Ua1n is the gate signal Ua2n is high for up counting and low for down counting. Count is synchronous with rising clock. FREQUENCY MEASUREMENT 7 1 1 1 Ua1n is frequency signal to be measured Ua2n is the gate signal of known time interval. Count is synchronous with rising edge of Ua1n. Table 1 Mode Description
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PE12316
PE12316 Triple Incremental Encoder
February 6, 2003 Preliminary (Version 1.1)
Detailed Information about the different Modes:
Mode 0: 16-Bit Up/Down Counter Mode In this mode the PE12316 may be used as three fast 16-bit synchronous up/down counters with cascade capability. This is operated using the /UP and /DOWN inputs. The states of the counter outputs are transferred to a 16-bit latch. The contents of this 16-bit latch are multiplexed on a 8-bit parallel data bus (D0...D7) and enabled using /RD and /CS. Channel number 1 2 3 No channel selected1 /A0 is the control input for the byte multiplexer. A high level at this input transfers the least significant byte to the data outputs; and a low level transfers the most significant byte. The signals /A1 and /A2 select the channel for read or write according to the following table.
/A1 H L H L
/A2 H H L L
Table 2 Channel Selection
1
Output buffers still selected if /RD and /CS active - data bus carries invalid data Cascading to 32, 40, 48 or 56 bits is possible by connecting the /CARRY, /BORROW outputs of channel n with the /UP, /DOWN Inputs of the channel n+1. In cascaded mode the according /KLI-KLOn have to be connected together. For further details see Application Notes.
The up/down counters are loaded in individual 8bit bytes by the /WR and /CS signals, with the byte selected by the /A0 input, and the channel by the /A1 and /A2 inputs. The counters and the control logic may be cleared all together using the /RESET signal. The counters are cleared individually using the /Ua0n signals. Memory Map: /A3 1* 1* 0 1* 1* 0 1* 1* 0 /A2 1 1 0 /A1 1 0 1
/A0 Channel 1 0 Channel 1 1 1 0 Channel 2 1 1 0 Channel 3 1
Content Bits 0-7 Bits 8-15 Bits 16-23 Bits 0-7 Bits 8-15 Bits 16-23 Bits 0-7 Bits 8-15 Bits 16-23
* Defaultvalue due to internal pullup
Table 3 Memory Map
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PE12316
PE12316 Triple Incremental Encoder
February 6, 2003 Preliminary (Version 1.1)
Mode 1-5: Direction Discriminator Modes The quadrature signals Ua1n and Ua2n, identify forward or backward directions. If Ua1n leads Ua2n, the forward direction is indicated and the counter will count up; if Ua1n lags Ua2n, the reverse direction is indicated and the counter will count down.
Figure 3 Direction Discriminator Modes
Ua1n and Ua2n are both stored in the first of a pair of consecutive D-type flip-flops on the clock falling edge, and transferred to the next on the clock rising edge.
By comparing the states of the four flip-flops and checking the mode inputs, the up or down count pulses are generated; see Figure 4 and Figure 5.
Figure 4 Direction Discriminator Up Clock
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PE12316 Triple Incremental Encoder
February 6, 2003 Preliminary (Version 1.1)
Figure 5 Direction Discriminator Down Clock MODES 1 to 5 define which edge of the quadrature signals will be counted in accordance with Table 1. The clock frequency should be at least four times greater than the frequencies of the quadrature signals. This will eliminate problems resulting from timing jitter in the transducer signals and will allow the quadruple counting mode to be used. The frequency of the quadrature signals, Ua1n and Ua2n may be calculated from the relationship:
F=
shaft _ speed resolution _ of _ transducer
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PE12316 Triple Incremental Encoder
February 6, 2003 Preliminary (Version 1.1)
MODE 6: Pulse Width Measurement Mode In this mode, Ua1n acts as a gate, and is the pulse width to be measured. Synchronised with the clock edge after a low to high transition in Ua1n, counting begins at the input clock frequency. Similarly, synchronised with the clock edge after a high to low transition of Ua1n, counting is disabled; the value in the counter is loaded in the output register; /KLI-KLOn is pulled low; and then the counter clears. See Figure 6. If Ua2n is held high, the counter will count up, and if Ua2n is held low, the counter will count down. Each counter can be preloaded in two or three bytes depending on 16 Bit or 24 Bit Mode by activating /CS, and /WE, and selecting the required byte with /A0 and /A3, and the required channel with /A1 and /A2. This must be done while Ua1n is low. The output register should be read by activating /CS, /RD, and selecting the individual bytes with /A0 after Ua1n has fallen and before the next preload takes place. The KLI-KLOn signal may be used as an interrupt to indicate to the processor when the output register has been loaded. In both the pulse width and frequency modes, the output register will not be loaded via /CS and /RD, but by the falling edge of Ua1n, or by pulling /KLI-KLOn low.
Figure 6 Pulse Width Measurement
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PE12316 Triple Incremental Encoder
February 6, 2003 Preliminary (Version 1.1)
MODE 7: Frequency Measurement Mode In Mode 7, Ua1n is the signal of unknown frequency to be measured; Ua2n is a gate signal of known width. A low to high transition of Ua2n enables counting at the frequency of Ua1n. When the gate (Ua2n) goes low, counting is disabled, the value of the counter is loaded into the output register, /KLI-KLOn is pulled low, and the counter is then cleared. See Figure 7.
Figure 7 Frequency Measurement
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PE12316 Triple Incremental Encoder
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Reset Operation:
A total reset is initiated by pulling the /RESET pin low. This will clear the counters to zero, reset the D flip-flops at the inputs of the quadrature signals (Ua1n and Ua2n), clear the latches that inhibit the load register pulse, and load zero into the output register. MODE 0 1-5 6-7 To avoid a spurious count error (+/- 1) after a reset, the Ua1n and Ua2n inputs should be held to the values indicated in Table 4 during and just after the reset pulse.
Ua1n X H L
Ua2n X H L
Table 4 Mode Selection
Cascading Devices
The /KLI-KLOn pins of all cascaded PE12316's should be tied together, so that all of the devices load their output registers at the same time. When the `Master' generates a pulse for the other PE12316s, /KLI-KLOn on the `Master' works as an output, and /KLI-KLOn on the `Slaves' work as inputs. The /CARRY output of one device should be tied to the /UP input of the next device in the cascade. Similarly, /BORROW should be connected to /DOWN. For details see Figure 14.
Write Operation
A number may be preloaded into the counter by pulling /CS and /WE low while using /A0 and /A3 to direct the value on the data bus to the selected byte of the counter and /A1 & /A2 to select the required channel. This will cause /READY to go low on the next falling clock edge, and remain low until /CS and /WE go high. See Figure 12.
Read Operation
When in Modes 0 to 5 the contents of the counter can be read at any time by pulling /CS and /RD low. The channel is selected by using /A1 & /A2. Within this channel the most significant byte may be selected by setting /A3 to low, and the least significant byte may be read by setting /A0 and /A3 high. This will cause a load output register pulse to be generated and /KLI-KLOn will go low during the next low clock pulse. /READY will also go low as the clock goes low, and will stay low until /CS and/or /RD go high. The load output register pulse stores the current value of the counter in a 16-bit latch register and /A0 /A3 direct the selected byte through a multiplexer to the outputs : /CS and /RD also enable the 3-stat outputs - see Figure 11. The output register will be loaded immediately if /KLIKLOn is pulled low externally, this signal normally comes from a cascaded device. For Modes 6 & 7 see the earlier description.
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PE12316 Triple Incremental Encoder
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Configuration
Special consideration should be paid to the automatic configuration features of the PE12316. The purpose of these features is to allow for the different order of byte reads (high then low or low then high) of different processors when doing a word read across a byte wide bus and also to configure cascaded devices automatically for correct word read sequence - see below.
Byte order Configuration
After a system reset has occurred, the first read operation will store the value of /A0 and /A3 in a latch within the device. From that time until the next system reset the load output register pulse during a read operation will only be generated if /A0 and /A3 are this stored value. This means that the internal load output register pulse is correctly generated for word operations regardless of the byte order of the particular processor. Special care should be taken if reading individual bytes to ensure these operations are always done in a consistent order.
Cascaded configuration
After a system reset the first device and channel to receive a read operation configures itself into `Master' mode and outputs a pulse on /KLI-KLO. In cascaded operation the /KLI-KLO pins of the cascaded channels are connected together and the input pulse on /KLI-KLO of the cascaded channels configures these to `Slave' mode. On all subsequent read operations the load output register pulse is only generated by the `Master' channel (for the appropriate polarity of /A0, as noted above) and this is fed to the `Slave' devices via the /KLI-KLO connection. Special care should be taken when cascading devices or channels to always read in the same channel order, as well as the byte order already mentioned. To freeze all three channels with a single read cycle (in cascaded or non-cascaded mode) the /KLI-KLOn pins of all channels are connected with a pull-up resistor to VCC (see System Application). This ensures that only one channel is operating as the `Master' and all others are `Slaves'. If an external "freeze" of the positioning system is required, an external /KLI-KLO pulse will program all channels as slaves. This is derived by generating an external /KLI-KLO pulse before the first read cycle appears after system reset.
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PE12316 Triple Incremental Encoder
February 6, 2003 Preliminary (Version 1.1)
Pin Description
Pin Name Pin Number 68 PLCC 12 8 I/O Description
/CS /RD
Input Input
Chip Select. A low enables the device. Read. When this and /CS are active (low), the data from the output register will be present on the data bus. LSB
D0 D1 D2 D3 D4 D5 D6 D7 /BORROW1 /BORROW2 /BORROW3 /CARRY1 /CARRY2 /CARRY3 /KLI-KLO1 /KLI-KLO2 /KLI-KLO3 /READY
14 15 17 18 20 21 23 24 58 56 54 59 57 54 62 61 60 63
Data Bus Buffer: Input/ 8-Bit Bi-directional Buffer with 3-state outputs Output connected to the microprocessor system. MSB Output Counter underflow signal.
Output Counter overflow signal. Input/ Cascade load input / cascade load output. Open Output drain (OD) output with internal 75kOhm (nom) pull(OD) up. External pull up required for full speed operation. Output When low signal indicates to the MPU that read or (OD) write may be completed. /READY falling edge synchronous with CLK Open Drain output needs external pull-up. Input Input Input Input Input Input Input Input Input Input Input Measuring input signals channel 1 (Schmitt-Trigger characteristics) Mode Select Inputs (see Table 1)
M21 M11 M01 M22 M12 M02 M23 M13 M03 Ua11 Ua21
29 28 27 34 32 30 37 36 35 39 41
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PE12316 Triple Incremental Encoder
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Pin Description
Pin Name Pin Number 68 PLCC Ua12 Ua22 Ua13 Ua23 /Ua01 /Ua02 /Ua03 CLK /A0 42 43 44 45 3 2 1 68 9 Input Input Input Input Input Input Input Input Input Measuring input signals channel 2 (Schmitt Trigger characteristics) Measuring input signals channel 3 (Schmitt Trigger characteristics) Zero pulse for each channel. When active (low), the counter in the appropriate channel is cleared. Other logic is not affected. (Schmitt Trigger characteristics) Clock. Used for internal synchronisation and control timing. (Schmitt Trigger characteristics) Byte select. A high level selects the least significant byte. A low level selects the most significant byte. Channel select. See Table 2 Selects Bits 16-23 of chosen channel. Internal Pullup. For details see Table 3 Memory Map. Device Reset. When active (low), the mode control logic is reset to a known state and the counter is cleared. (Schmitt Trigger characteristics) Write enable. When /WE and /CS are active (low), the data that is on the bus is loaded into the counter addressed by /A0, /A1, /A2 and /A3. Cascade Input for counting down. I/O Description
/A1 /A2 /A3 /RESET
10 11 6 5
Input Input Input Input
/WE
7
Input
/DOWN1 /DOWN2 /DOWN3 /UP1 /UP2 /UP3 VCC GND
47 49 51 46 48 50 16,22, 52,66 13,19, 25,53, 64
Input Input Input Input Input Input
Cascade Input for counting up.
Power Supply voltage Ground
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PE12316 Triple Incremental Encoder
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Absolute Maximum Ratings over operating free air temperature:
Symbol Parameter VCC DC Supply Voltage VIN DC Input Voltage IIN DC Input Current Storage Temperature (Plastic Package) Value -0.3 to + 7.0 -0.3 to VCC + 0.3 +/- 10 -40 to +125 Units V V mA C
DC Characteristics (referred to GND):
Symbol VOH Parameter Output High Level Test Condition IOH = -20 uA IOH = -8 mA, VCC = 5.0V IOH = -6 mA, VCC = 3.3V Output Low Level Input High Level Input Low Level Supply current Schmitt Trigger positive going threshold Schmitt Trigger negative going threshold Schmitt Trigger Hysteresis Tristate Output Leakage Current
Input High current Input with pullup
Min VCC-0.1 2.4 2.4
Typ
Max
Units V V V
All except, /READY and /KLI-KLO
All except D0-D7, /READY and /KLI-KLO
VOH D0-D7 VOH VOL VIH VIL ICC VT+ VTVHYS IOZ IIH IIL
IOH = 20 uA TTL Schmitt Trigger 20 MHz VCC=Max VCC = Min to Max VCC = Min to Max VCC = Min to Max VCC = Max or GND VIN = VCC VIN = GND 0.2 -10 -10 -200 -10 2.0 2.4
0.1
V V
0.5 25 2.4 0.5
V mA V V V
+10 +10 -10 +10
uA uA uA uA
Input Low current
Recommended Operating Conditions:
Symbol VCC VCC TAC Parameter DC Supply Voltage DC Supply Voltage (Low Power Application) Temperature Range Value 4.5 to 5.5 3.0 to 3.6 0 to +70 Units V V C
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PE12316 Triple Incremental Encoder
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Timing Requirements over Recommended Operating Conditions
Symbol Tc1 Tc2 Twrs fmud Twud Twk Twrd1 Twrd2 Tdrd Twwr Tdwr Tsd Tsus Tsa Tsud Tsab Tsda Tsbb Tsac Tsar Tsbc Tsr Tsuc Thdw Twgp Twgp Tdgp Pulse width low CLK Pulse width, /RESET input low Maximum frequency, /UPn or /DOWNn, Input duty cycle 50% Pulse width, /UPn or /DOWNn input low Pulse width, /KLI-KLOn input low Pulse width, /RD input low (Mode = 6 & 7) Pulse width, /RD input low (Mode = 0 to 5) Time between two read cycles (LSB and MSB) Pulse width, /WE input low Time between two read cycles (LSB and MSB) Set up time, DATA prior to /WE rising Set up time, /CS and /RD low before CLK falling edge Set up time, /A0, /A1, /A2 prior to /WE and /CS low Set up time, /UPn or /DOWNn rising edge before CLK falling edge Set up time, Ua1n or Ua2n prior to CLK falling edge. Set up time, DATA prior to /WE rising Set up time, Ua2n stable before CLK falling edge Set up time, Ua1 or Ua2 rising edge before CLK falling edge. Set up time, /A0, /A1, /A2 stable before /CS and /RD low after reset Set up time, Ua1n or Ua2n falling edge Set up time, /RESET high prior to CLK falling edge. Set up time, /UPn or /DOWNn rising edge prior to /KLI-KLOn (input) falling edge. Hold time DATA after /WE rising Pulse width, Ua1n input high (Mode = 6) Pulse width, Ua2n input high (Mode = 7) Pulse width, Ua1n input low (Mode = 6) 0 25 0 15 15 10 20 15 Tsd 15 15 10 15 0 20 10 Min 2 x Tc1 Min 2 x Tc1 Min 2 x Tc1 Tc1 Parameter CLK Cycle Time, duty cycle 50% MIN 50 25 50 20 25 20 25 TYP MAX Units ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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PE12316 Triple Incremental Encoder
February 6, 2003 Preliminary (Version 1.1)
Timing Requirements over Recommended Operating Conditions - continued
Symbol Tdgf Tha Thab Thda Thac Thbc Twrn Parameter Pulse width, Ua2n input low (Mode = 7) Address hold time after /WE or /CS high Ua1n or Ua2n hold time after CLK falling edge D0-D7 hold time after /A0 change Ua1n high hold time after CLK falling edge Ua2n hold time after CLK falling edge Pulse width, /Ua0n input low 12 12 10 12 12 5 MIN TYP Min 2 x Tc1 MAX Units ns ns ns ns ns ns ns
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PE12316 Triple Incremental Encoder
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Switching Characteristics, (VCC= Min, Temperature +70 Degrees)
Symbol Tdd1 Parameter Access time, /RD and CLK to data output valid (Mode = 0 to 5) Access time, /RD to data output valid Mode = 0 to 5 2nd byte Mode = 6-7 both bytes Propagation delay /RD, /WE or From CS /CS inactive to /READY Propagation delay CLK to /READY low Propagation delay /UPn or /DOWNn rising edge to /CARRYn or /BORROWn rising edge From /UPn to /CARRY Test Conditions MIN TYP MAX 65 Units ns
Tdd2
45
ns
Thdr Tdr
20 30
ns ns
Tduc
35
ns
Tdcc
From /CLK to Propagation delay from CLK to /CARRY or /CARRYn or /BORROWn rising edge from /CLK to /BORROW Propagation delay CLK falling edge to /KLI-KLOn falling edge Propagation delay CLK rising edge to /CARRYn or /BORROWn rising edge Enable Time /RD and /CS low to D0-D7 /KLI-KLOn low output pulse width /CARRYn or /BORROWn low output pulse width /CARRYn or BORROWn low output pulse width Release time, DATA after /RD, /CS 0 Tc2 Twud Tc2 From /CLK to /CARRY or /BORROW
25
ns
Tdco Tdcb Ted Twco Twcb Twcc Thdr
55 25 65
ns ns ns ns ns ns
45
ns
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February 6, 2003 Preliminary (Version 1.1)
Figure 9 Timing - all modes
Figure 8 Timing -Mode 1 - 5
Figure 10 Timing - Mode 6-7
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PE12316 Triple Incremental Encoder
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Figure 11 Read Cycle
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Figure 12 Write Cycle
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PE12316 Triple Incremental Encoder
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System Application
Figure 13 shows a three axis microcomputer system using the PE12316. The clock of the microcomputer can be used to drive the PE12316 and addressing is either via memory mapped I/O or external I/O port addresses. The basic timing cycle must be chosen so that it matches that of the PE12316 read and write timing. In Mode 0, all Ua1n's and Ua2n's must be connected to VCC. In all other modes /UPn and /DOWNn are tied to VCC. If a parallel freeze of all three channels is required all /KLI-KLOn's are connected together. One external pull-up (6.8k - 12k) is required in this case. If the UaXn input are not used, they must be tied to VCC. Figure 13 shows the Mode 5 connection for quadruple count inputs of Ua1n and Ua2n.
A0...A15
Address BUS
8-Bit MicroController
CS
D0...D7 RD Reset Clk WD
8-Bit DATA BUS
4 Vcc
RD WE RESET SystemRESET
CS
D0...D7
A0-A3 UPn DOWNn
CLK M01 /02 /03 M21 /22 /23 M11 /12 /13 Ua01 Ua11 Ua21 KLI-KLO1
PE12316
10k Ua02 Ua12 Ua22 KLI-KLO2 Ua03 Ua13 Ua23 KLI-KLO3
FREEZE
Axis 1
Axis 2
Axis 3
Figure 13 Three Axis Control System using PE12316
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Cascading to 32 Bits
D0...D7(MSB) CS A0/1/2/3 RD WR CLK
4
8-Bit Data Bus
Vcc 4
CS UP1 Ua11 Ua01 Ua21 Ua11 Ua01 Ua21
CLK
D0...D7
A0...A3
RD WE CARRY1
CS UP2 Ua12
CLK
D0...D7
A0...A3
RD WE CARRY2 CAR
1/3 PE12316 (LS-Word)
READY
Ua02 Ua22
1/3 PE12316 (MS-Word)
READY
DOWN1 KLI-KLO M01 M11 M21
BORROW1 RESET
DOWN2 KLI-KLO 10k M02 M12 M22
BORROW2 RESET
BOR
10k READY RESET FREEZE
Figure 14 Two Cascaded Channels (One 32-bit channel shown) In systems requiring a higher resolution, two PE12316's or two channels of the PE12316 can be cascaded to achieve 32 bit accuracy Figure 14 shows the block diagram of this application. It shows the two PE12316 devices with one channel of each cascaded to 32 bit. The LS-word PE12316 is operating in Mode 5 and the MS-word in Mode 0 (count only). The /KLI-KLO signals of each channel are connected together with a pull up of 10k and can be used as an external freeze input. In this case, the first external /KLI-KLO pulse, programming the PE12316 into the SLAVE mode, must occur before the first read cycle, otherwise the device channel receiving the first read cycle will be programmed into the master mode and generate a /KLI-KLO pulse for the second device. /UP1 and /DOWN1 of the first device are tied to Vcc. Both /Ua01's are connected together and can recover the zero pulse from the resolver.
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PE12316 Triple Incremental Encoder
February 6, 2003 Preliminary (Version 1.1)
The system reset inputs of each PE12316 device (/RESET) are connected together and must be used to ensure that the system is started from a known state after the power-up. If /READY is used from the PE12316, both are wired-OR and a pull-up of 10k is connected to VCC to generate a proper high level in the non-active state (open drain output).
February 6, 2003 (Preliminary Version 1.1)
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PE12316
PE12316 Triple Incremental Encoder
February 6, 2003 Preliminary (Version 1.1)
PLCC68 Package Dimensions Package Drawing:
Figure 15 PLCC68 Package Dimension
February 6, 2003 (Preliminary Version 1.1)
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PE12316
PE12316 Triple Incremental Encoder
February 6, 2003 Preliminary (Version 1.1)
IMPORTANT NOTICE Productivity Engineering GmbH (PE) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to PE's terms and conditions of sale supplied at the time of order acknowledgment. PE warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with PE's standard warranty. Testing and other quality control techniques are used to the extent PE deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. PE assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using PE components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. PE does not warrant or represent that any license, either express or implied, is granted under any PE patent right, copyright, mask work right, or other PE intellectual property right relating to any combination, machine, or process in which PE products or services are used. Information published by PE regarding third-party products or services does not constitute a license from PE to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from PE under the patents or other intellectual property of PE. Resale of PE products or services with statements different from or beyond the parameters stated by PE for that product or service voids all express and any implied warranties for the associated PE product or service and is an unfair and deceptive business practice. PE is not responsible or liable for any such statements.
Mailing Address:
Productivity Engineering GmbH Behringstr. 7 D-71083 Herrenberg Germany Phone: (+49) 7032 / 2798-0 Fax: (+49) 7032 / 2798-29 email: info@pe-gmbh.com
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PE12316
PE12316 Triple Incremental Encoder
February 6, 2003 Preliminary (Version 1.1)
Application Notes:
24 Bit Access To provide 24 Bit counting on each channel, /A3 on pin 6 is introduced. However it has to be kept in mind for cascading that /CARRY, /BORROW are derived from bits 0-15 of the counter to ensure compatibility with CF32006. The first channel in the chain can only be 16 bit wide to provide the correct interfacing signals CARRY/BORROW to the following channel. However the last channel in the chain can use the full 24 bit. /A3 is located on pin 6 which is an "NC" pin on CF32006. This pin was not allowed to have a connection to the PCB board. Therefore no compatibility issue should arise. As with all other addresslines, /A3 is low active. An internal pullup resistor ensures that /A3 can be left unconnected, if the 24 bit feature is not used. For details see Table 3 Memory Map. Possible Cascading Combinations: First channel 16 Bit 16 Bit 16 Bit 16 Bit Second channel 16 Bit 24 Bit 16 Bit 16 Bit Third channel none none 16 Bit 24 Bit Resulting bitwidth 32 Bit 40 Bit 48 Bit 56 Bit
Table 5 Cascading bitwidths Read Cycle: The Readcycle is intended and designed synchronous to the clock. Special care has to be taken for the parameter Tsus ( the setup time of the falling edge of /RD before the falling CLK edge). If Tsus is not within spec, there is the possibility that the output register is not updated and the same value will be read twice. Therefore the microprocessor system collecting the data and PE12316 should either have the same clock or the /RD on the PE12316 has to be synchronized into the PE12316 clock domain via an ACT74 Type Flipflop. Electrical Design Recommendations: It is recommended that the PE12316 is used without a socket and with at least 4 decoupling capacitors (100 nF) connected to VCC and GND close to the package.
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PE12316
PE12316 Triple Incremental Encoder
February 6, 2003 Preliminary (Version 1.1)
Figures
Figure 1 Pinout............................................................................................................................ 1 Figure 2 Block Diagramm for 16 Bit Mode................................................................................... 4 Figure 3 Direction Discriminator Modes...................................................................................... 7 Figure 4 Direction Discriminator Up Clock.................................................................................. 7 Figure 5 Direction Discriminator Down Clock ............................................................................. 8 Figure 6 Pulse Width Measurement............................................................................................. 9 Figure 7 Frequency Measurement............................................................................................. 10 Figure 10 Timing - Mode 6-7 ..................................................................................................... 19 Figure 11 Read Cycle ................................................................................................................ 20 Figure 12 Write Cycle ................................................................................................................ 21 Figure 13 Three Axis Control System using PE12316 ............................................................... 22 Figure 14 Two Cascaded Channels (One 32-bit channel shown) .............................................. 23 Figure 15 PLCC68 Package Dimension ..................................................................................... 25
Tables
Table 1 Mode Description............................................................................................................ 5 Table 2 Channel Selection........................................................................................................... 6 Table 3 Memory Map ................................................................................................................... 6 Table 4 Mode Selection ............................................................................................................. 11 Table 5 Cascading bitwidths ..................................................................................................... 27
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PE12316
PE12316 Triple Incremental Encoder
February 6, 2003 Preliminary (Version 1.1)
Contact Information:
For ordering and sample requests: Adronic Components GmbH Bodelschwinghstr. 32 D-75031 Eppingen Germany Phone: (+49) 7262 / 912360 Fax: (+49) 7262 / 912361 email: info@adronic.de
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PE12316

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